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<a href="#nested-classes">Data Structures</a> &#124;
<a href="#enum-members">Enumerations</a>  </div>
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<div class="title">Generic Clock Management</div>  </div>
<div class="ingroups"><a class="el" href="group__clk__group.html">Clock Management</a></div></div>
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<table class="memberdecls">
<tr><td colspan="2"><h2><a name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structgenclk__config.html">genclk_config</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Hardware representation of a set of generic clock parameters.  <a href="structgenclk__config.html#details">More...</a><br/></td></tr>
<tr><td colspan="2"><h2><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__genclk__group.html#gaca55f4f4f96549b8111139d144bce01c">genclk_source</a> { <br/>
&#160;&#160;<a class="el" href="group__genclk__group.html#ggaca55f4f4f96549b8111139d144bce01ca953707a1c76a0268413b7232d99d0065">GENCLK_SRC_RCSYS</a> =  0, 
<a class="el" href="group__genclk__group.html#ggaca55f4f4f96549b8111139d144bce01ca3d1fd9213fb1acca868f9aed0580080f">GENCLK_SRC_OSC32K</a> =  1, 
<a class="el" href="group__genclk__group.html#ggaca55f4f4f96549b8111139d144bce01caeb9bb887118c6aaf7a1c193f80205909">GENCLK_SRC_RC8M</a> =  2, 
<a class="el" href="group__genclk__group.html#ggaca55f4f4f96549b8111139d144bce01ca885a673e1f2c68e84f6461cb38d2e50f">GENCLK_SRC_OSC0</a> =  3, 
<br/>
&#160;&#160;<a class="el" href="group__genclk__group.html#ggaca55f4f4f96549b8111139d144bce01ca2c0a57ce35b0fa7efac9930357278930">GENCLK_SRC_OSC1</a> =  4, 
<a class="el" href="group__genclk__group.html#ggaca55f4f4f96549b8111139d144bce01ca4db9dbbdde9e4efb5b26e8ddfe817812">GENCLK_SRC_PLL0</a> =  5, 
<a class="el" href="group__genclk__group.html#ggaca55f4f4f96549b8111139d144bce01ca229fcad1bdb8ec267a05a8f1d1b0491e">GENCLK_SRC_PLL1</a> =  6, 
<a class="el" href="group__genclk__group.html#ggaca55f4f4f96549b8111139d144bce01cac903dd8fc4bf4fbdfa810ab774035a1b">GENCLK_SRC_CLK_CPU</a> =  7, 
<br/>
&#160;&#160;<a class="el" href="group__genclk__group.html#ggaca55f4f4f96549b8111139d144bce01ca5bb1dbdcf7db89069ddcc2a59d36a6b6">GENCLK_SRC_CLK_HSB</a> =  8, 
<a class="el" href="group__genclk__group.html#ggaca55f4f4f96549b8111139d144bce01ca0647cd0e7fc56115d0003306568c29ff">GENCLK_SRC_CLK_PBA</a> =  9, 
<a class="el" href="group__genclk__group.html#ggaca55f4f4f96549b8111139d144bce01ca956d2618a06550aba0d3c2c1cd784be9">GENCLK_SRC_CLK_PBB</a> =  10, 
<a class="el" href="group__genclk__group.html#ggaca55f4f4f96549b8111139d144bce01ca73e71d3958e85af71ec37d4e2ca76c54">GENCLK_SRC_CLK_PBC</a> =  11
<br/>
 }</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Generic clock source ID.  <a href="group__genclk__group.html#gaca55f4f4f96549b8111139d144bce01c">More...</a><br/></td></tr>
<tr><td colspan="2"><h2><a name="member-group"></a>
Chip-specific generic clock definitions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__genclk__group.html#gada51baf0de37e57d7052f6f6ea324b53">GENCLK_DIV_MAX</a>&#160;&#160;&#160;256</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum divider supported by the generic clock implementation.  <a href="#gada51baf0de37e57d7052f6f6ea324b53"></a><br/></td></tr>
</table>
<hr/><a name="details" id="details"></a><h2>Detailed Description</h2>
<p>Generic clocks are configurable clocks which run outside the system clock domain. They are often connected to peripherals which have an asynchronous component running independently of the bus clock, e.g. USB controllers, low-power timers and RTCs, etc.</p>
<p>Note that not all platforms have support for generic clocks; on such platforms, this API will not be available. </p>
<hr/><h2>Define Documentation</h2>
<a class="anchor" id="gada51baf0de37e57d7052f6f6ea324b53"></a><!-- doxytag: member="uc3c/genclk.h::GENCLK_DIV_MAX" ref="gada51baf0de37e57d7052f6f6ea324b53" args="" -->
<div class="memitem">
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          <td class="memname">#define GENCLK_DIV_MAX&#160;&#160;&#160;256</td>
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<p>Maximum divider supported by the generic clock implementation. </p>

</div>
</div>
<hr/><h2>Enumeration Type Documentation</h2>
<a class="anchor" id="gaca55f4f4f96549b8111139d144bce01c"></a><!-- doxytag: member="uc3c/genclk.h::genclk_source" ref="gaca55f4f4f96549b8111139d144bce01c" args="" -->
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          <td class="memname">enum <a class="el" href="group__genclk__group.html#gaca55f4f4f96549b8111139d144bce01c">genclk_source</a></td>
        </tr>
      </table>
</div>
<div class="memdoc">

<p>Generic clock source ID. </p>
<p>Each generic clock may be generated from a different clock source. These are the available alternatives provided by the chip. </p>
<dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"><em><a class="anchor" id="ggaca55f4f4f96549b8111139d144bce01ca953707a1c76a0268413b7232d99d0065"></a><!-- doxytag: member="GENCLK_SRC_RCSYS" ref="ggaca55f4f4f96549b8111139d144bce01ca953707a1c76a0268413b7232d99d0065" args="" -->GENCLK_SRC_RCSYS</em>&nbsp;</td><td>
<p>System RC oscillator. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="ggaca55f4f4f96549b8111139d144bce01ca3d1fd9213fb1acca868f9aed0580080f"></a><!-- doxytag: member="GENCLK_SRC_OSC32K" ref="ggaca55f4f4f96549b8111139d144bce01ca3d1fd9213fb1acca868f9aed0580080f" args="" -->GENCLK_SRC_OSC32K</em>&nbsp;</td><td>
<p>32 kHz oscillator </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="ggaca55f4f4f96549b8111139d144bce01caeb9bb887118c6aaf7a1c193f80205909"></a><!-- doxytag: member="GENCLK_SRC_RC8M" ref="ggaca55f4f4f96549b8111139d144bce01caeb9bb887118c6aaf7a1c193f80205909" args="" -->GENCLK_SRC_RC8M</em>&nbsp;</td><td>
<p>8 MHz RC oscillator </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="ggaca55f4f4f96549b8111139d144bce01ca885a673e1f2c68e84f6461cb38d2e50f"></a><!-- doxytag: member="GENCLK_SRC_OSC0" ref="ggaca55f4f4f96549b8111139d144bce01ca885a673e1f2c68e84f6461cb38d2e50f" args="" -->GENCLK_SRC_OSC0</em>&nbsp;</td><td>
<p>Oscillator 0. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="ggaca55f4f4f96549b8111139d144bce01ca2c0a57ce35b0fa7efac9930357278930"></a><!-- doxytag: member="GENCLK_SRC_OSC1" ref="ggaca55f4f4f96549b8111139d144bce01ca2c0a57ce35b0fa7efac9930357278930" args="" -->GENCLK_SRC_OSC1</em>&nbsp;</td><td>
<p>Oscillator 1. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="ggaca55f4f4f96549b8111139d144bce01ca4db9dbbdde9e4efb5b26e8ddfe817812"></a><!-- doxytag: member="GENCLK_SRC_PLL0" ref="ggaca55f4f4f96549b8111139d144bce01ca4db9dbbdde9e4efb5b26e8ddfe817812" args="" -->GENCLK_SRC_PLL0</em>&nbsp;</td><td>
<p>PLL 0. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="ggaca55f4f4f96549b8111139d144bce01ca229fcad1bdb8ec267a05a8f1d1b0491e"></a><!-- doxytag: member="GENCLK_SRC_PLL1" ref="ggaca55f4f4f96549b8111139d144bce01ca229fcad1bdb8ec267a05a8f1d1b0491e" args="" -->GENCLK_SRC_PLL1</em>&nbsp;</td><td>
<p>PLL 1. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="ggaca55f4f4f96549b8111139d144bce01cac903dd8fc4bf4fbdfa810ab774035a1b"></a><!-- doxytag: member="GENCLK_SRC_CLK_CPU" ref="ggaca55f4f4f96549b8111139d144bce01cac903dd8fc4bf4fbdfa810ab774035a1b" args="" -->GENCLK_SRC_CLK_CPU</em>&nbsp;</td><td>
<p>CPU clock. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="ggaca55f4f4f96549b8111139d144bce01ca5bb1dbdcf7db89069ddcc2a59d36a6b6"></a><!-- doxytag: member="GENCLK_SRC_CLK_HSB" ref="ggaca55f4f4f96549b8111139d144bce01ca5bb1dbdcf7db89069ddcc2a59d36a6b6" args="" -->GENCLK_SRC_CLK_HSB</em>&nbsp;</td><td>
<p>High Speed Bus clock. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="ggaca55f4f4f96549b8111139d144bce01ca0647cd0e7fc56115d0003306568c29ff"></a><!-- doxytag: member="GENCLK_SRC_CLK_PBA" ref="ggaca55f4f4f96549b8111139d144bce01ca0647cd0e7fc56115d0003306568c29ff" args="" -->GENCLK_SRC_CLK_PBA</em>&nbsp;</td><td>
<p>Peripheral Bus A clock. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="ggaca55f4f4f96549b8111139d144bce01ca956d2618a06550aba0d3c2c1cd784be9"></a><!-- doxytag: member="GENCLK_SRC_CLK_PBB" ref="ggaca55f4f4f96549b8111139d144bce01ca956d2618a06550aba0d3c2c1cd784be9" args="" -->GENCLK_SRC_CLK_PBB</em>&nbsp;</td><td>
<p>Peripheral Bus B clock. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="ggaca55f4f4f96549b8111139d144bce01ca73e71d3958e85af71ec37d4e2ca76c54"></a><!-- doxytag: member="GENCLK_SRC_CLK_PBC" ref="ggaca55f4f4f96549b8111139d144bce01ca73e71d3958e85af71ec37d4e2ca76c54" args="" -->GENCLK_SRC_CLK_PBC</em>&nbsp;</td><td>
<p>Peripheral Bus C clock. </p>
</td></tr>
</table>
</dd>
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